CS Core & Software Engineering · Computer Architecture
Input, Output and DMA
How the CPU talks to devices: polling, interrupts, DMA, and the same LOAD aimed at a device register.
So far 0x1000 was a word in memory. Sometimes the address in R2 names a device register — a disk controller, a network card — not a DRAM word. This topic is how the CPU talks to those devices: waiting on each byte, being interrupted, or letting DMA copy a block while the CPU runs other instructions.
- CS Core & Software Engineering
- Hard level
- 5 concepts
1Why devices are a different path
A 2 GHz CPU, the clock from the iron-law example, issues a tick every 0.5 ns. A mechanical disk still takes milliseconds to find a sector. Even a fast SSD is tens to hundreds of microseconds. If the CPU treated a device like a register and waited, those milliseconds would become millions of wasted cycles — the pipeline we just built would sit idle on purpose.
I/O is the path that lets a slow device finish without freezing that pipeline. The ISA may still use a LOAD; the destination is no longer DRAM.
Figure. A CPU tick versus a 5 ms device wait. Heights are schematic: an honest 10-million-to-one ratio cannot be drawn, so the ledger carries the cycle count.
How it works
- CPU tick2 GHz → 0.5 ns per clock. The iron law's clock lever.
- Device waitA 5 ms disk seek is 0.005 s — millions of those ticks if the CPU spins.
- I/O pathA way for the device to finish without occupying every one of those ticks.
Cycles wasted on a 5 ms wait
The CPU runs at 2 GHz. A disk seek takes 5 ms. How many clock cycles pass if the CPU waits the whole seek?
- Clock frequency2 \times 10^9 cycles/s
- Seek = 5 ms0.005 s
- Cycles = 2 \times 10^9 \times 0.00510^7 = 10 million
Pro tip. Ten million cycles of a 5-stage pipe is ten million issue slots. That is why programmed waiting is the last resort, not the default.
A 2 GHz CPU that busy-waits a 5 ms device operation wastes about
- 10 million cycles
- 5 cycles
- 2 million cycles
2 \times 10^9 \times 0.005 = 10^7. Five cycles is one instruction's pipeline latency. 2 million would be a 1 ms wait at 2 GHz.
2Programmed I/O
Programmed I/O, or polling, is the simplest device path. The CPU writes a command to the device, then repeatedly reads a status register until the device says it is done, then copies the data. Every check is an instruction. The CPU is occupied for the whole wait — those 10 million cycles from the previous concept.
If 0x1000 were a status register instead of a price, a loop of `LOAD R1, (R2)` would spin until the value in R1 changed. Same ISA instruction; the microarchitecture is talking to a device, and the program is wasting the pipeline on purpose.
Figure. The CPU issues LOAD after LOAD to the status register. Until the device replies "done", every pipeline issue slot belongs to that loop.
How it works
- CommandCPU writes a command to the device.
- PollCPU repeatedly LOADs a status register until the device says done.
- CopyCPU reads or writes the data. It was occupied for the whole wait.
Programmed I/O (polling) keeps the CPU
- Busy checking status until the device finishes
- Free to run other instructions during the wait
- Idle in a power-gated sleep that a device cannot wake
Polling is a spin loop of LOADs. Interrupts (next) free the CPU during the wait. Sleep that cannot be woken would miss the completion.
3Interrupts
An interrupt lets the device signal the CPU when it is done. The CPU writes the command, then goes back to useful work — other instructions, other programs. When the interrupt arrives, the CPU saves its place, runs a short handler that reads the data, and returns. The LOAD of the status or data register happens in the handler, not in a spin loop.
Interrupts do not make the device faster. They make the CPU free during the wait. The 5 ms seek still takes 5 ms; the pipeline is no longer spent polling it.
Figure. The CPU starts the device and returns to other work. The dashed edge is the later interrupt — one signal, not a spin of LOADs.
How it works
- StartCPU writes the command, then runs other instructions.
- SignalDevice raises an interrupt when it is done.
- HandlerCPU saves its place, runs a short handler that reads the data, and returns.
| Path | CPU during wait | How completion is seen |
|---|---|---|
| Programmed I/O | Spinning on status | LOAD returns "done" |
| Interrupt | Running other work | Handler runs, then LOAD |
Switching from polling to interrupts on a 5 ms disk seek
- Frees the CPU during the seek; the seek still takes 5 ms
- Cuts the seek to a few microseconds
- Removes the need for any LOAD of device data
The device is not faster. The CPU stops spending 10 million cycles on a spin loop. The handler still LOADs the data when the interrupt arrives.
4Direct memory access
Direct memory access, DMA, is for a block, not a status bit. The CPU tells a DMA controller "copy 4 KB from this device into memory at this address", then goes back to the program. The controller moves the bytes on the memory bus. When the copy finishes, the controller interrupts once. The CPU never executes a LOAD per byte.
On a 100 MB/s bus, 4 KB takes about 41 μs of bus time. A programmed loop that spent 1 μs of CPU time per 4-byte word would occupy the CPU for 1024 μs — about 25 times longer — and the pipeline would be busy the whole time. DMA does not shrink the device; it shrinks the CPU's involvement.
Figure. The CPU only sets up the controller. The block copy runs between device and memory. The CPU is not on that edge — that is the whole point of DMA.
How it works
- SetupCPU tells the DMA controller: source, destination, byte count.
- CopyThe controller moves the bytes on the memory bus. The CPU is not in that loop.
- DoneOne interrupt when the block is in memory. No LOAD per byte.
4 KB on a 100 MB/s bus
A DMA transfer copies 4096 bytes on a 100 MB/s bus. A programmed loop would spend 1 μs of CPU time on each 4-byte word. Compare the DMA bus time with that CPU occupancy.
- Bus rate100 \times 10^6 B/s
- DMA time = 4096 / 10^84.096 \times 10^{-5} s = 40.96 μs
- Programmed words = 4096 / 41024 words
- Programmed CPU time = 1024 × 1 μs1024 μs ≈ 25 × DMA bus time
Pro tip. 40.96 μs is bus occupancy, not a claim that the disk finished in 41 μs. The 25× is CPU time saved, which is the point of DMA.
DMA is preferable to programmed I/O when
- A block of bytes must move and the CPU has other work
- The device only ever returns one status bit
- The ISA has no LOAD instruction
DMA pays setup cost to move a block without a LOAD per byte. A single status bit is what polling or one interrupt already handles. DMA does not replace the ISA.
5Memory-mapped I/O
Memory-mapped I/O puts device registers in the same address space as DRAM. `LOAD R1, (R2)` is the same ISA instruction either way. If R2 holds a device address instead of 0x1000-in-DRAM, the memory stage talks to the device, not to the cache/DRAM path. Isolated (port) I/O uses special IN/OUT instructions instead; the program can see that ISA difference.
The cache must not treat a device register as a cacheable DRAM line. A status register can change without any store from this CPU — the device wrote it. Caching that line would serve a stale "not yet" forever. The running LOAD is unchanged in the ISA; the address it names decides whether MEM is a cache walk or a device register.
Figure. The same LOAD forks. The solid edge is the cache/DRAM path from the memory topic. The dashed edge is a device register — same instruction, different MEM destination, and that destination is not a cache line.
How it works
- Same LOADLOAD R1, (R2) is still the ISA instruction. R2 may now hold a device address.
- Memory-mappedDevice registers live in the same address space as DRAM. The MEM stage talks to the device.
- Do not cacheA device register can change without a store. The cache must not treat it as a DRAM line.
| R2 names | MEM stage | Cache? |
|---|---|---|
| DRAM word 0x1000 | Cache, then DRAM on miss | yes |
| Device status register | Device, not DRAM | no — would go stale |
LOAD R1, (R2) when R2 names a device status register should
- Bypass the cache — the register can change without a store
- Use the same cache line as 0x1000 — a load is a load
- Be rejected by the ISA — LOAD is only for DRAM
Memory-mapped I/O reuses LOAD. Caching a device register is the bug: the device updates it without a CPU store. The ISA does not forbid LOAD to that address.
Notes
- A 2 GHz CPU waiting 5 ms burns about 10 million cycles — devices need a path that does not occupy the pipeline.
- Programmed I/O (polling) spins on a status register; the CPU is busy for the whole wait.
- Interrupts free the CPU during the wait; they do not make the device faster.
- DMA copies a block between device and memory after a setup; the CPU is not in the per-byte loop.
- Memory-mapped I/O reuses LOAD/STORE; device registers must not be cached as DRAM lines.
Formulas
- Busy-wait cycles ≈ clock frequency × device wait time.
- DMA bus time ≈ bytes / bus bandwidth.
- Programmed CPU occupancy ≈ (bytes / word size) × time per programmed word.
Exam traps & shortcuts
- Interrupts save CPU time, not device time.
- DMA is for blocks; polling or one interrupt is enough for a status bit.
- A LOAD to a device address is still a LOAD — do not cache it.
Reference tables
Pick the path by what is moving and whether the CPU has other work.
| Path | CPU during transfer | Best for |
|---|---|---|
| Programmed I/O | Spinning | A status bit, or a tiny transfer |
| Interrupt | Other work, then a handler | Completion of a wait |
| DMA | Other work after setup | A block of bytes |
Recap
Devices are slow. Free the CPU. Reuse LOAD only if the line is not cached.
- Gap
- 2 GHz × 5 ms = 10 million cycles if the CPU waits.
- Poll
- LOAD status in a loop. Simple, and it occupies the pipe.
- Interrupt
- Device signals done. Does not shorten the seek.
- DMA
- Setup, then a block copy. 4 KB @ 100 MB/s ≈ 41 μs of bus, not of CPU.
- mmap
- Same LOAD; device registers are not cacheable DRAM.
Practise Input, Output and DMA
Reading is free and needs no account. Practice, mocks and progress live in the app.
- A 4-question practice set that ends the chapter
- 5 quick checks with worked explanations
- Timed mocks scored with the real marking scheme
- Readiness tracked per topic, kept on your device