ISA and CPU Time

1ISA versus microarchitecture

The instruction set architecture, or ISA, is the contract a program is written against: the registers it may name, the instructions it may use, and what each instruction is required to do. Microarchitecture is how one particular chip implements that contract — a five-stage pipeline, a cache, a 2 GHz clock. Two chips can share one ISA and differ in every one of those implementation choices.

The ISA does not mention cache lines or pipeline stages. Those are microarchitectural. Change the pipeline and keep the ISA, and old programs still run. Change the ISA, and they do not — the compiler would have to emit different instruction bits.

Figure. The left box is the contract the program sees. The right box is how one chip keeps that contract. The running LOAD is the same instruction on both sides.

How it works

1. ISAThe names the program may use: registers, opcodes, and what each instruction must do.
2. MicroarchitectureThe chip's implementation: pipeline, cache, clock — invisible to the binary.
3. Same binaryTwo chips that share an ISA run the same LOAD R1, (R2); they may take different time.

2CPU time — the iron law

CPU time is how long the processor spends on a program. It is the product of three independent levers: \text{CPU time} = \text{Instruction count} \times \text{CPI} \times \text{Clock cycle time}. Instruction count is how many instructions actually run. CPI, cycles per instruction, is the average number of clock ticks each of those instructions occupies. Clock cycle time is the length of one tick — at 2 GHz that tick is 0.5 ns.

Halving any one factor halves total time. A better compiler that emits fewer instructions moves the first lever. A pipeline that overlaps work moves CPI. Faster silicon moves the clock. Exam questions and design reviews both ask which lever a change actually moved — not whether "the computer got faster" in the abstract.

Figure. Three multiplicative factors. The bar heights are not a measured program — they mark that each lever is independent. Cut any one, or improve another enough to compensate.

How it works

1. Instruction countHow many instructions the program executes — algorithm and compiler, and which ISA they target.
2. CPIAverage clock cycles per instruction — pipelining lowers it toward 1; hazards raise it.
3. Clock cycle timeSeconds per cycle — a 2 GHz clock is 0.5 ns per tick.

3One instruction: LOAD R1, (R2)

The running example for this course is one instruction: `LOAD R1, (R2)`. The parentheses mean "use R2 as a pointer". The CPU reads the address stored in R2 — we will use 0x1000 — then reads the word at that address into register R1. That whole action is one instruction in the ISA, so it adds 1 to the iron law's instruction count.

A different ISA might need two instructions to do the same job (compute an address, then load). That is how ISA design moves the instruction-count lever. The later topics keep this same LOAD: a pipeline will overlap its stages, a cache will sit under its memory read, and an I/O path appears if 0x1000 names a device register instead of a DRAM word.

Figure. R2 supplies the address 0x1000. Memory returns the word stored there. R1 receives that word. One ISA instruction, two hardware reads: the register, then the memory word.

How it works

1. Read R2R2 holds an address. In this course that address is 0x1000.
2. Read memoryThe CPU reads the word stored at 0x1000.
3. Write R1That word is copied into R1. The instruction count for this line is 1.

The running instruction

LOAD R1, (R2)   ; R2 holds 0x1000
; R1 ← memory[0x1000]

4Addressing modes

An addressing mode is the rule the ISA uses to form the effective address of an operand — the actual location the instruction will read or write. Immediate embeds a constant in the instruction bits. Direct writes a memory address into the instruction. Register uses a register as the operand. Register-indirect, the mode of `LOAD R1, (R2)`, uses a register as a pointer to memory. Indirect goes one step further: the instruction names a memory word that itself holds the address. Indexed adds a displacement to a base register, the usual pattern for `a[i]`.

The mode decides how many memory references the instruction needs after it has been fetched. Immediate and register need zero data fetches. Our LOAD needs one. Memory-indirect needs two: fetch the pointer, then fetch the operand.

Figure. Addressing modes differ in how the effective address is computed. The middle box is our running LOAD: R2 already holds 0x1000, so the effective address is the contents of R2.

How it works

1. Immediate / registerOperand is in the instruction or a register — no extra memory fetch for the data itself.
2. Direct / register-indirectDirect names a memory address in the instruction. Register-indirect, our LOAD, names a register that holds the address.
3. Indirect / indexedIndirect fetches a pointer from memory first. Indexed adds a displacement to a base register, typically for an array.

5One instruction, five jobs

Before overlapping anything, picture `LOAD R1, (R2)` occupying the whole machine. Fetch reads the instruction bits from memory at the program counter. Decode reads the opcode and the two register numbers. Execute forms the effective address 0x1000 from R2. Memory reads the word at 0x1000. Write-back copies that word into R1. In a non-pipelined machine the next instruction does not start until write-back finishes.

Those five jobs are why a five-stage pipeline can help: each job becomes a stage, and the next instruction can start its fetch while this LOAD is still in memory. That overlap is the next topic. The ISA has not changed — the same LOAD still means the same thing.

Figure. Five jobs in order for a single LOAD. MEM is the read at 0x1000; WB writes R1. Nothing else is in the machine until WB finishes.

How it works

1. FetchRead the instruction bits at the program counter.
2. DecodeRead the opcode and register numbers — LOAD, R1, R2.
3. ExecuteForm the effective address from R2: 0x1000.
4. MemoryRead the word at 0x1000.
5. Write-backPut that word in R1. Only then may the next instruction start.